In order to successfully coherently recover data from a received digital communication signal, digital communication receivers employ some form of clock recovery mechanism that operates on the received signal to regenerate the embedded clock signal. As diagrammatically illustrated in FIG. 1, the clock and data transport path often include a first-in, first-out (FIFO) buffer 10, which receives a serial data stream 11 that is synchronous with an incoming clock signal 12. Because the data is not necessarily continuous (namely, a new piece of data is not always available at each clock cycle of the recovered clock), a valid data signal 13 indicating when the data is valid is provided to the buffer.
The output end 14 of the buffer is coupled to a downstream digital device 15, which requires the generation of an output or read clock 16 that matches the effective data rate, but without gaps such as may be associated with times of the input clock for which there is no valid data. This allows data to be read out from the buffer at each clock cycle of the newly generated clock. This new clock and the data can then be successfully delivered to the next portion of the downstream digital transport path. Conventional approaches to solving this problem involve dividing a high-speed clock down to the necessary frequency, or the use of an external phase locked loop.